Modern integrated circuits are made up of literally millions of active devices, such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an input/output (I/O) pad. An UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in that order, on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Recently, copper pillar bump technology has been proposed. Instead of using a solder bump, a given electronic component is connected to a substrate by means of a copper post, which achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits, and allows the electronic component to perform at higher frequencies.
Thermal stress problems that have been observed in testing and in use after assembly in completed flip chip packages using the copper posts include delamination of extreme low-k (ELK) dielectric layers, cracks in the underfill material, the passivation layer, and pre-solder materials due to the above materials being near to the copper posts and subject to substantial thermal stress during thermal cycles. As the size of the integrated circuit devices continues to shrink, the pitch between the terminals and the corresponding copper posts will also continue to decrease. The problems associated with the thermal stresses observed using the copper posts may be expected to increase with continued reduction in the pitch between terminals. In conventional approaches to integrated circuit flip chip package assembly with a conventional copper post, a single photoresist film (a dry film or a wet film) with photolithography process is employed to define a window on the UBM layer, and then a copper layer is plated therein to form a copper post with a vertical or negative sidewall profile. However, it is difficult to enlarge the bottom dimension of the copper post. The stress in the extreme low-k dielectric layers cannot be shared by an interface between the UBM layer and the passivation layer. A need thus exists for improved integrated circuit flip chip connections, such as copper posts to solve the problems caused by thermal stress.